The host schedules the transfers on the bus. A USB 2.0 host controller manages traffic by dividing time into 1-ms frames at low and full speeds and 125-µs microframes at high speed. The host allocates a portion of each (micro)frame to each transfer. Each (micro)frame begins with a Start-of-Frame (SOF) timing reference. The SuperSpeed bus doesn’t use SOFs, but a USB 3.0 host schedules SuperSpeed transfers within 125-µs bus intervals. A USB 3.0 host also sends timstamp packets once every bus interval to all SuperSpeed ports that aren’t in a low-power state.
Each transfer consists of one or more transactions. Control transfers always have multiple transactions because they have multiple stages, each consisting of one or more transactions. Other transfer types use multiple transactions when they have more data than will fit in a single transaction. Depending on how the host schedules the transactions and the speed of a device’s response, the transac tions in a transfer may all be in a single (micro)frame or bus interval, or the transactions may be spread over multiple (micro)frames or bus intervals.
Every device has a unique address assigned by the host, and all data travels to or from the host. Except for remote wakeup signaling, everything a USB 2.0 device sends is in response to receiving a packet sent by the host. Because multiple devices can share a data path on the bus, each USB 2.0 transaction includes a device address that identifies the transaction’s destination.SuperSpeed devices can send status and control information to the host without waiting for the host to request the information. Every SuperSpeed Data Packet and Transaction Packet includes a device address. SuperSpeed also uses Link Management Packets packets that travel only between a device and the nearest hub and thus don’t need addressing information.
