Archive for the ‘USB’ Category
Endpoint Zero Configured
Posted by Parkzone Corsair in USB on December 16th, 2009
Every USB transfer consists of one or more transactions, and each transaction in turn contains packets of information. To understand transactions, packets, and their contents, you also need to understand endpoints and pipes. So that’s where we’ll begin.All bus traffic travels to or from a device endpoint. The endpoint is a buffer that typically stores multiple bytes and consists of a block of data memory or a register in the device-controller chip. The data stored at an endpoint may be received data or data waiting to transmit.
The host also has buffers that hold received data and data waiting to transmit, but the host doesn’t have endpoints.Instead, the host serves as the source and destination for communications with device endpoints.An endpoint address consists of an endpoint number and direction. The number is a value in the range 0–15. The direction is defined from the host’s perspective: an IN endpoint provides data to send to the host and an OUT endpoint stores data received from the host. An endpoint configured for control transfers must transfer data in both directions, so a control endpoint consists of a pair of IN and OUT endpoint addresses that share an endpoint number.
Every device must have endpoint zero configured as a control endpoint. There’s rarely if ever a need for additional control endpoints.
Transaction Packet includes a device address
Posted by Parkzone Corsair in USB on December 16th, 2009
The host schedules the transfers on the bus. A USB 2.0 host controller manages traffic by dividing time into 1-ms frames at low and full speeds and 125-µs microframes at high speed. The host allocates a portion of each (micro)frame to each transfer. Each (micro)frame begins with a Start-of-Frame (SOF) timing reference. The SuperSpeed bus doesn’t use SOFs, but a USB 3.0 host schedules SuperSpeed transfers within 125-µs bus intervals. A USB 3.0 host also sends timstamp packets once every bus interval to all SuperSpeed ports that aren’t in a low-power state.
Each transfer consists of one or more transactions. Control transfers always have multiple transactions because they have multiple stages, each consisting of one or more transactions. Other transfer types use multiple transactions when they have more data than will fit in a single transaction. Depending on how the host schedules the transactions and the speed of a device’s response, the transac tions in a transfer may all be in a single (micro)frame or bus interval, or the transactions may be spread over multiple (micro)frames or bus intervals.
Every device has a unique address assigned by the host, and all data travels to or from the host. Except for remote wakeup signaling, everything a USB 2.0 device sends is in response to receiving a packet sent by the host. Because multiple devices can share a data path on the bus, each USB 2.0 transaction includes a device address that identifies the transaction’s destination.SuperSpeed devices can send status and control information to the host without waiting for the host to request the information. Every SuperSpeed Data Packet and Transaction Packet includes a device address. SuperSpeed also uses Link Management Packets packets that travel only between a device and the nearest hub and thus don’t need addressing information.
Vendor Can Also Define Requests
Posted by Parkzone Corsair in USB on December 16th, 2009
USB supports four transfer types: control, bulk, interrupt, and isochronous. In a control transfer, the host sends a defined request to the device. On device attachment, the host uses control transfers to request a series of data structures called descriptors from the device. The descriptors provide information about the device’s capabilities and help the host decide what driver to assign to the device.
A class specification or vendor can also define requests. Control transfers have up to three stages: Setup, Data (optional), and Status. The Setup stage contains the request. When present, the Data stage contains data from the host or device, depending on the request. The Status stage contains information about the success of the transfer. In a control read transfer, the device sends data in the Data stage. In a control write transfer, the host sends data in the Data stage, or the Data stage is absent.
The other transfer types don’t have defined stages. Instead, higher-level software defines how to interpret the raw data. Bulk transfers are the fastest on an otherwise idle bus but have no guaranteed timing. Printers and USB virtual COM-port data use bulk transfers. Interrupt transfers have guaranteed maximum latency, or time between transaction attempts. Mice and keyboards use interrupt transfers. Isochronous transfers have guaranteed timing but no error correcting. Streaming audio and video use isochronous transfers.
